The present invention claims priority under 35 U.S.C. xc2xa7119 to Korean Application No. 02-10205 filed on Feb. 26, 2002, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and a semiconductor device, and more particularly to a method for fabricating a semiconductor device, and a semiconductor device, having storage node contact plugs.
2. Description of the Related Art
In a dynamic random access memory (DRAM), which is a semiconductor device having a capacitor over bit-line (COB) structure in which capacitors are formed after bit lines are formed, storage node contact holes for forming storage node contact plugs are formed between narrow bit lines, and thus the size of the storage node contact holes is small. In addition, the storage node contact holes must be formed by deeply etching an interlayer dielectric (ILD) film, and thus it is very difficult to form the storage node contact holes. In particular, a highly developed alignment technique is required during a photolithographic process. Since the alignment margin is less than 30 nm in a process having a design rule less than 0.15 xcexcm, it is very difficult to form the storage node contact holes so that the same design rule is obtained in every process.
In order to form the storage node contact holes so that same design rule is obtained in every process, a process of forming self-aligned contact holes has been suggested. In the process of forming self-aligned contact holes, an ILD film having different etch selectivity with respect to a silicon nitride layer is etched after bit lines are covered with the silicon nitride layer, to thereby form storage node contact holes that are self-aligned in the silicon nitride layer. However, since the silicon nitride layer becomes thinner as the design rule becomes smaller, the occurrence of shorts between a storage node contact plug and a bit line increases as the thickness of the silicon nitride layer approaches zero.
As the aspect ratio of the storage node contact holes becomes larger, the storage node contact holes are not completely formed (or so-called not-open), or the width of the storage node contact holes becomes smaller in the lower portions of the storage node contact holes to thus be tapered. In either case, contact area between the storage node contact plugs and conductive regions under the storage node contact plugs (such as cell pads) becomes smaller, and thus contact resistance is greatly increased.
The present invention is thus directed to a method for fabricating a semiconductor device, and a semiconductor device, having storage node contact plugs, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an object of the present invention to provide a method for fabricating a semiconductor device, and a semiconductor device, whereby storage node contact plugs are formed so that the occurrence of shorts between the storage node contact plugs and bit lines are greatly reduced and sufficient contact area between the storage node contact plugs and cell pads is obtained.
Accordingly, to achieve the above object, there is provided a method for fabricating a semiconductor device, including forming bit lines on a semiconductor substrate on which cell pads are formed, the cell pads being separated from each other by an insulating layer; forming a bit line protection layer on an entire surface of the semiconductor substrate having the bit lines formed thereon, the bit line protection layer having a thickness so that the bit lines are not buried; forming a first interlayer dielectric (ILD) film on the bit line protection layer, the first ILD film having a flat top and a thickness which is equal to or greater than a height of the bit lines; forming a second ILD film on the first ILD film; the second ILD film having a wet etch rate smaller than a wet etch rate of the first ILD film; forming storage node contact holes having narrow width by dry etching the second and first ILD films between the bit lines, the storage node contact holes exposing the cell pads; increasing the width of the storage node contact holes by wet etching the second and first ILD films, so that a lower width of each of the storage node contact holes is increased relatively more than an upper width of each of the storage node contact holes in view of the wet etch rates of the first and second ILD films; forming insulating layer spacers on internal walls of the storage node contact holes; and forming separated storage node contact plugs by burying a conductive material in the storage node contact holes in which the insulating layer spacers are formed.
The second ILD film is formed as having a thickness smaller than that of the first ILD film.
The first ILD film is formed of an insulating material in which impurities are doped with a first concentration, and the second ILD film is formed of the insulating material in which impurities are doped with a second concentration lower than the first concentration. The impurities are selected from the group consisting of boron (B) and phosphor (P). The insulating material may be an oxide in which the impurities are doped. The impurity-doped insulating material may be boron silicate glass (BSG), phosphorus silicate glass (PSG), or boron phosphorus silicate glass (BPSG).
The first ILD film may be formed of BSG, PSG, or BPSG, and the second ILD film may be formed of tetra ethyl ortho silicate (TEOS), or an oxide that is formed by high density plasma-chemical vapor deposition (HDP-CVD).
The first ILD film is etched using the bit line protection layer as an etch stopper, whereby the lower width of each of the storage node contact holes is increased. The forming of the first ILD film includes forming an insulating layer as having a thickness larger than the height of the bit lines to bury the bit lines on the semiconductor substrate on which the bit line protection layer is formed, and chemical mechanical polishing the insulating layer using the bit line protection layer as an etch stopper.
The bit line protection layer is formed of silicon nitride. The bit lines are formed by sequentially stacking a bit line conductive layer and a capping layer.
The first ILD film is formed as having a thickness larger than the height of the bit lines, and the second ILD film is completely removed during forming of the insulating layer spacer.
The forming of the insulating layer spacer includes forming an insulating layer for spacing on an entire surface of the semiconductor device after said increasing the width of the storage node contact holes, the insulating layer for spacing having a thickness so that the storage node contact holes are not buried; and anisotropically etching the insulating layer for spacing while protecting the first ILD film and the insulating layer for spacing formed on sidewalls of the first ILD film, so that the insulating layer for spacing remains only on the internal walls of the storage node contact holes, the upper width of each of the storage node contact holes being relatively narrower than the lower width of each of the storage node contact holes, so that the second ILD film overhangs the first ILD film and the insulating layer for spacing formed on the sidewalls of the first ILD film, to protect the first ILD film and the insulating layer for spacing during said anisotropically etching. In a case where the first ILD film is formed as having a thickness larger than the height of the bit lines, the second ILD film is completely removed during anisotropically etching the insulating layer for spacing.
The forming of the storage node contact plugs includes depositing the conductive material on an entire surface of the semiconductor device after said forming insulating layer spacers, so that the storage node contact holes on which the insulating layer spacers are formed are completely buried; and planarizing a top surface of the semiconductor device after said depositing the conductive material, until the second ILD film is exposed. In a case where the first ILD film is formed to a thickness larger than the height of the bit lines, the second ILD film is completely removed during planarizing the top of the resultant structure on which the conductive material is deposited.
In order to achieve the above objects, there is also provided a semiconductor device including a substrate having cell pads formed thereon, the cell pads being separated from each other by insulation material; bit lines disposed on the substrate; a bit line protection layer disposed on an entire surface of the semiconductor device including the bit lines and the substrate, the bit line protection layer having a thickness so that the bit lines are not buried; a first interlevel dielectric (ILD) layer disposed on the bit line protection layer, the first ILD layer having a thickness such that areas between the bit lines are buried and the bit line protection layer on top surfaces of the bit lines are exposed; a second interlevel dielectric (ILD) layer disposed on the first ILD layer and the exposed bit line protection layer; storage node contact holes disposed in between the bit lines through the second and first ILD layers and the bit line protection layer to the cell pads, a lower width of the storage node contact holes through the first ILD layer being greater than an upper width of the storage node contact holes through the second ILD layer; and a conductive material buried within the storage node contact holes.
According to the present invention, the occurrence of shorts between storage node contact plugs and bit lines may be greatly reduced and sufficient contact area between storage node contact plugs and cell pads is obtained, so that increases in contact resistance can be effectively prevented. Since the upper width of each of the storage node contact holes is relatively narrower than the lower width of each of the storage node contact holes, the first ILD film and the insulating layer for spacing that is formed on the sidewall of the first ILD film can be protected during anisotropic etching of the insulating layer for spacing that forms the insulating layer spacer.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.